Staff Physical Design Engineer, STA

Mountain View, CA
Silicon /
/ Hybrid
About us:
Aeva’s mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions.
Role Overview:
Aeva is seeking a Physical Design engineer with strong experience in Static Timing Analysis. In this role, you will be responsible for the timing analysis methodology, implementation, and sign-off for Aeva digital ASICs.

What you'll be doing:

    • You are expected to have hands-on experience with most aspects of physical implementation including Synthesis, Static Timing Analysis, and post-silicon timing characterization.
    • Drive the timing analysis methodology for pre-layout and post-layout implementation activities for blocks and at full-chip level with a good understanding of PPA trade-offs.
    • Work closely with 3rd party IP vendors on proper SDC generation for the IPs and close timing at IP and chip-level
    • Collaborate with implementation engineers and designers in SDC generation and verification using industry-standard tools.
    • Be a clear communicator with a proven ability to work across functions inside the company, and with partners across the globe. Lead by example in a fast-paced environment.

What you'll have:

    • Extensive experience in timing closure of multiple ASICs to production in advanced process nodes
    • Experience working with high-performance designs, identifying strategies to close aggressive timing targets
    • Must have worked with 3rd party mixed-signal IP vendors and resolved timing challenges
    • Hands-on experience with Synthesis, STA. Developed timing methodologies and flows using industry-standard tools with automation.
    • Experience in post-silicon timing characterization across corners
    • BSEE, MSEE, or Ph.D. with 15+ years of relevant experience in physical implementation of Digital ASICs.

Nice to haves:

    • Familiarity with developing automotive grade silicon with AEC-Q100 qualification and ISO 26262

What's in it for you:

    • Be part of a fast-paced and dynamic team
    • Very competitive compensation and meaningful stock grants
    • Exceptional benefits: Medical, Dental, Vision, and more
    • Unlimited PTO: We care about results, not punching time cards.