RTL Verification Engineer

San Francisco, CA /
Electronics & Electrical Engineering – Payload /
Full-time
Astranis is connecting the four billion people in the world who do not currently have access to the internet. We are building the next generation of smaller, lower-cost spacecraft to bring the world online.

We are well-funded by some of the best investors in the business and have raised over $350 million to date. We have a world-class team that is passionate about building amazing technology. And we have a fun and collaborative work environment where you will learn a lot and make a huge impact no matter where you are in your career. Just check out our Glassdoor reviews to see what our team has to say about working at Astranis.

Our team is growing fast. Apply now!

As an RTL verification engineer at Astranis, you will be responsible for developing and maintaining the FPGA simulation and verification infrastructure at Astranis, develop BFM and test benches. Also you’ll be involved in the drafting of test plans, tracking bugs, and supporting RTL design engineers in troubleshooting design problems. You'll support the rest of the FPGA team in testing the design, collecting coverage reports, and you'll help improve and maintain our FPGA image release process.

Role

    • Develop and maintain RTL simulation and regression tests for FPGAs.
    • Develop BFM’s and simulation test benches, and maintain automatic regression tests.
    • Responsible for implementing FPGA regression tests, reporting and tracking bugs, and FPGA release tracking.
    • Help lead the simulation/verification infrastructure.
    • Support the development of a hardware-based regression/continuous integration setup.
    • Assist in recruiting, interviewing, and hiring additional teammates to our rapidly-growing team.

Requirements

    • 5+ years of professional experience.
    • Familiarity with SystemVerilog, SystemVerilog assertions, and SystemVerilog constrained randomization.
    • Experience with Python or similar scripting languages such as tcl, bash, csh, or Perl.
    • Extensive experience in either FPGA or ASIC verification (or both)
    • Experience with C/C++, SystemVerilog DPI, and related software build tools (GNU gcc/make)

Bonus

    • Experience in UVM (or OVM/VMM/AVM/Specman)
    • Experience with existing regression tools, to automatically track bugs (e.g., coverage aggregation tools or similar)
U.S. Citizenship, Lawful Permanent Residency, or Refugee/Asylee Status Required
(To comply with U.S. Government space technology export regulations, applicant must be a U.S. citizen, lawful permanent resident of the United States, or other protected individual as defined by 8 U.S.C. 1324b(a)(3))
 
Our mission and our products are meant to connect the world and everyone in it, regardless of gender, race, creed, or any other distinction. We believe in a diverse and inclusive workplace, and we encourage all people to join our team and bring their unique perspective to help make us stronger.