Execute floor-planning and layout of block and chip-level designs in a variety of semiconductor Integrated chip technologies.

Support full chip integration & mask-reticle assembly.

2+ years of experience in physical layout design across a variety of silicon and III-V semiconductor IC technologies. 

Experience with Cadence Virtuoso, Calibre DRC/LVS/LPE, Assura. Must be able to resolve LVS/DRC errors. 

Knowledge of deep sub-micron layout design practices such as metal density rules, transistor, and capacitor matching.

Ability to communicate effectively with circuit designers to flow down layout requirements.

Experience customizing and generating standard cells for automated digital design flows is a bonus.

BS or MS., Electrical Engineering, Computer Science, or Related Discipline

U.S. citizenship is required.

Must be able to obtain and maintain a security clearance.

Active SSBI is a plus.

The base salary range for this full-time position is $99,705 - $124,683 + bonus + benefits.

Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range during the hiring process. Please note that the compensation details listed reflect the base salary only, and do not include potential bonus or benefits.

We are proud to be an EEO/AA employer M/F/D/V. We maintain a drug-free workplace and perform pre-employment substance abuse testing.