Chip Lead
Bay Area
Engineering /
Full-time /
On-site
Join the leading chiplet startup! As an Eliyan chip lead, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be developing chip micro-architecture specifications for best-in-class PHYs and Controllers. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.
Key Responsibilities
- Support micro-architecture development working with marketing and architecture teams
- Collaborate with system architects to define chip functionality, interfaces, and performance targets
- Collaborate with cross-functional design teams (digital design, verification, DFT, analog and packaging) to define chip and block partitions
- Responsible for chip level micro-architecture specifications
- Responsible for 3rd party IP evaluation and arrive at a plan of record for execution vis-à-vis power, area, performance and schedule
- Work closely with physical design team for physical implementation
- Oversee all aspects of the chip execution through tape-out and bring-up
- Define production and bench-level test plans
- Stay up to date with industry trends, emerging technologies and progress in standards’ bodies
Qualifications
- Bachelors or Masters or Ph.D in Electrical Engineering and related fields, or equivalent
- 12+ years of experience in high-speed digital design (preferably in retimer, gearbox, Ethernet PMA/PCS logic)
- Strong understanding of digital and analog design principles, expertise in RTL based digital IC design using SystemVerilog
- Proficiency in synthesis and implementation tools (Synopsys or Cadence)
- Experience with 3rd party high-speed interface IPs and low-speed IO interface Ips
- Excellent problem-solving skills and attention to details
- A self-starter with the ability to assume technical leadership in exploring new design paradigms
- Knowledge of Ethernet 802.3 standards’ clauses related to 100G/200G/400G/800G, Auto-Negotiation and Link Training
- Strong bias for innovations across all aspects of digital design including automation of mundane activities and methods for quality improvement
- Expertise in Forward Error Correction (FEC) code implementation and performance analysis
- Proven track record of being part of a start-up like environment
- Knowledge of DRAM Controllers/PHYs and HBM Memory a plus
