Principal FPGA Design Engineer

Plano, TX /
Engineering & Technology – 5G Digital Design /
Full-Time
Wireless technology now impacts nearly every aspect of daily life around the world.  As the fastest-growing global tech company, JMA designs and delivers cutting-edge wireless technology solutions that modernize how people learn, work, live and play, like never imagined. We power today’s leading industries through next generation software-based 5G, private wireless networks, 5G-ready antennas and connectors, and advanced indoor 5G capabilities — all manufactured in the U.S.  Our headquarters, along with the first-of-its-kind 5G campus are located in Syracuse, NY, with innovative tech hubs around the world. Join our team to shape the future of wireless technology and elevate how people experience the world!    

JMA Wireless has an opening for a Principal FPGA Design Engineer- 5G Wireless to work in our Plano, Texas office.
Engineer will work on FPGA developments for 4G and 5G base stations and radios. Working with a dynamic team locally and across different locations, the engineer will define requirements, architecture, design, and implement multiple product features. Success depends on collaboration in planning, execution with architecture, digital RTL design, hardware board design, verification, and system level testing. 

Requirements

    • BS/MS in Electrical Engineering and/or Computer Engineering, Computer Science or similar 
    • Minimum 10 years of high-end FPGA development experience
    • Proficiency in Verilog, SystemVerilog, and VHDL
    • Propose and drive the architecture for design/implementation to fulfill the product requirements
    • Must have strong background in Xilinx FPGA and/or Altera/Intel FPGA  design flow: Quartus, Vivado tool, tcl scripting, timing closure backend, and Signaltap, Chipsope debug.
    • Familiar with testbench environment and the verification tools such as Modelsim, Questa.
    • Experience with high speed network protocols (QSFP+,USB, ETH), SERDES interfaces (JESD204B, 10G/25G GbE), PTP IEEE1588 time synchronization, bus interfaces (AXI, Avalon, PCIe) and memories (DDR, QDR)
    • Experience with lab bring-up procedure, lab equipment and troubleshooting
    • Knowledge of Telecommunication, Digital Signal Processing, and Cellular standards

Responsibilities

    • Work with team members to propose and drive the high level and micro-architect, Design, development, implementation FPGA features
    • Use Verilog/SystemVerilog and/or VHDL to implement the sub-modules and integrate them into FPGA top level
    • Write block-level testbenches along with stimuluses to verify the written RTL modules
    • Work with hardware-board-design engineer to assist in FPGA pin-out and pin selection process
    • Assist in hardware activities; board bring-up and debug, validation.  Responsible for HW bring-up to make sure all major interfaces (such as DDR4, 10G/25G GbE, JESD204B, PCIe, PTP synchronization, etc) around FPGA interfaces work as expected
    • Evaluate and profile FPGA vendor IPs
    • Responsible for the maintenance of FPGA including feature enhancements, performance increases, troubleshooting, testing, and bug fixing
    • Work closely with other software and hardware engineers to solve design issues 
    • Work with HW engineers for efficient interfaces ensuring system functionality 
    • Participate in board design schematic reviews ensuring proper connectivity for system level features 
    • Deliver high-quality tests for the individual modules and the overall system 
    • Providing technical documentation (test procedures, design specifications, etc.) 
    • Be involved in the full life-cycle of test development from concept through integration and test deployment 
    • Interface with mechanical, hardware board, and software teams 
    • Special projects as assigned 

Preferred Qualifications

    • Cocotb and/or UVM for verification
    • Experience with source-code revision control (such as Git BitBucket) in the team-based development environment
    • Experience with Jira Sprint planning and working flow
    • Plus to have any of the following areas:
    • LDPC encoder/decoder
    • Polar encoder/decoder. 
    • RE mapper/demapper design. 
    • HARQ combining. 
    • MIMO Detection.
    • Channel Estimation/Equalization. 
    • Control or Data channels debug. 
    • Frequency, Time domain - xFFT  
    • Any relevant debug in modem area. 

    • #LI-DD1
JMA offers a total rewards package designed to support your life, both in and outside of work.  When you join our team, you have immediate access to numerous benefits and perks that fit your specific needs. Whether you're looking for employee discounts, financial, legal and/or childcare resources and support, we have you covered! We believe in providing comprehensive health and wellness coverage along with monetary rewards towards health goals, in addition to numerous company-provided personal protection benefits at no additional cost to you. Investing in our employees is our #1 priority.  Are you in?

At JMA Wireless, we don’t just accept differences — we celebrate, support, and thrive on them for the benefit of our employees, our products, and our community. JMA Wireless is proud to be an equal opportunity workplace. We do not discriminate based upon race, religion, color, national origin, gender (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristic.