CPU Microarchitect

San Jose, CA /
Engineering /
Full time
/ Remote
Seeking experienced Microarchitect Lead Engineer. Responsible for leading and owning RTL development of one or more modules of a high-performance CPU core. Hands-on working knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU core is required. The candidate will be responsible for all aspects of the design including Performance, Power, and Area.

Minimum Qualifications

Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas:
-Instruction fetch and decode, branch prediction
-Instruction scheduling and register renaming
-Out-of-order execution
-Integer and Floating-point execution
-Load/Store execution, prefetching
-Cache and memory subsystems
Knowledge of Verilog and/or VHDL
Experience with simulators and waveform debugging tools.
Knowledge of logic design principles along with timing and power implications
MS degree in Electrical or Computer Engineering with 5+ years or BS degree with 7+ years of practical experience

Preferred Qualifications

Experience with designing RISC-V, ARM, and/or MIPS CPU
Experience with Hardware multi-threading, virtualization, and SIMD designs
Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
Understanding of low-power microarchitecture techniques
Experience using a scripting language such as Perl or Python

Roles and Responsibilities

Drive the micro-architecture and design of a critical CPU block or multiple blocks of a CPU core.
Performance exploration- explore high-performance strategies working with the CPU modeling team
Microarchitecture development and specification- from early high-level architectural exploration, through microarchitectural research and arriving at detailed specifications
RTL ownership- configurable Design Features Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
Functional verification support- assist the design verification strategy.
Performance verification support- assist with the verification of RTL design performance goals
Design delivery- partner with a multi-functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power