IC Layout Mask Designer
Layout Design /
IC layout designer will be responsible for layout of cutting edge high performance, high speed CMOS integrated circuits in foundry CMOS process nodes in 7nm, 16nm, 28nm, 40nm and 65nm following best practices from the industry. Job requirements include the following qualifications.
- Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.
- Experience with layout of high performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc. desired.
- Knowledge of high performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration.
- Knowledge of skill code and layout automation a plus.
- Self starter with the ability to define and adhere to a schedule.
- Must possess strong written and verbal communication skills.
- 3+ years experience in high performance analog layout in advanced CMOS process.