RTL Design Engineer
San Francisco Bay Area /
Hardware Engineering /
REX Computing is developing the future of massively parallel and high density computing systems that target the high performance computing (HPC) and server marketplaces. REX has developed a new highly scalable processor and system level compute node architecture with a focus on providing superior energy efficiency (performance per watt) in comparison to solutions provided by both market incumbents and competing startups alike. Our architecture relies on densely packed, custom processor chips and is designed to enable a large amount of computing performance while offering extreme power efficiency, scalability, and practical programmability.
More information in our press release :
We are seeking candidates that are exceptionally hands on, are comfortable in designing from the ground up, and are passionate about computer architecture and hardware development.
We are open to both to candidates with relevant academic backgrounds and to seasoned professionals. We also encourage hardware hackers and tinkerers to apply.
In addition to base pay, we offer comprehensive health, dental, and vision insurance in addition to an attractive equity package.
- Define and own micro-architecture of our highly scalable system
- Own RTL implementation, logic synthesis, and timing closure of design
- Participate in and/or oversee physical design through foundry hand off
- Collaborate with verification team for pre- and post- silicon debug
- Contribute to overall system architecture
- Hands on coding ability with SystemVerilog, Verilog, and C
- Skilled with scripting languages such as Python and Perl
- Domain specific experience in computer architecture
- Possesses very good oral and written communication skills
- Excited to work in a seed-funded startup environment
- Experience prototyping and debug using FPGA platform
- Hands on experience with RTL to GDS-II flow
- Knowledge of techniques for chip-to-chip communication
- Experience with low-power techniques such as clock gating