Silicon Packaging Designer (Interposer, Substrate) - Full Time
(US) Santa Clara CA , Austin TX, Portland OR, Fort Collins CO
Engineering – Platform Engineering (HW) /
Full-time /
The individual in this role is responsible for designing interposer, substrate or capacitor technology designs and tapeout.
Responsibilities
- Work with cross-functional teams to select the optimized package solution
- Work with IC design, system design, package SI/PI & thermal engineering teams to design custom interposer and substrates.
- Work with SoC design teams to optimize die floorplan, bump patterns and interposer / substrate stackup.
- Own package design deliverables at critical design checkpoints and tape out of package to vendors.
Requirements
- Experience on interposer and substrate layouts and design in advanced package technologies.
- Experience with 2.5D, 3D package design.
- Experience with design teams on floor plan, bump and layout optimization.
- Strong authority on Cadence Allegro Package Designer (APD)Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
- Ability to work well in a team and be productive under aggressive schedules.
Education and Experience
- Master’s Degree with 10+ years of experience in technical subject area
We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.