I/O Subsystem Architect

(US) Santa Clara CA , Austin TX, Portland OR, Fort Collins CO
Engineering – SOC/uncore Architecture /
Full-time /
Hybrid
Our mission is to create computing platforms using workload-driven HW/SW co-design that will transform the industry with the most advanced technologies. As I/O subsystem architect, you will be responsible for the architecture specification for external interfaces and their performance, power, area requirements. This will cover both Ethernet and PCIe/CXL subsystems for Datacenter products. You will be working with the Silicon team (eg. RTL/microarchitecture, DV, PD, Perf, DFT) members, the Platform team (board/system design, SI/PI), the Workload analysis team, the Software team and industry consortiums such as UEC and PCI-SIG.

Responsibilities

    • As a I/O Subsystem Architect, you will own or participate in the following: 
    • Architecture development and specification - from early high-level architectural exploration through micro architectural direction and writing a detailed specification
    • Memory (PCIe/CXL) and Network (Ethernet) style I/O subsystems, their connection to the internal fabric, RAS and Security requirements, bandwidth and latency targets
    • Development, assessment, and refinement of Architecture to target power, performance, area, and timing goals
    • Helping produce and review validation plans for functionality and performance

Requirements

    • This is an architecture lead position so a senior level of experience is expected.
    • Thorough knowledge of I/O Subsystem architecture
    • Experience with high bandwidth Ethernet NIC and/or PCIe Ports (and prepared to provide architecture leadership for interfacing to both)
    • Experience with Datacenter class RAS, QoS and Security (working with the security team)
    • Knowledge of on-chip network protocols: AMBA, AXI, CHI, ACE, Tilelink or APB. 
    • Experience with RDMA, RoCEv2, or Infiniband is useful
    • Experience with SERDES based PHYs, or Die-to-die (eg UCIe) is useful
    • Experience with system-level network topologies such as rings, mesh, torus, fat-trees is useful
    • Knowledge of cache coherent memory systems and interconnect is useful
    • Knowledge of SystemVerilog or Verilog, C or C++, scripting languages such as Python
    • Experience with functional and performance simulators
    • Knowledge of logic design principles along with timing and power implications
    • Understanding of low power architecture techniques
    • Understanding of high performance techniques and trade-offs for I/O

Education and Experience

    • Industry experience as well as PhD, Master’s Degree or Bachelor’s Degree in a technical subject area.