Memory Subsystem Intern

Santa Clara, CA
Engineering – Silicon Engineering /
Intern /
Our mission is to create computing platforms (HW/SW co-design) that will transform the industry with the most advanced technologies. As a memory subsystem intern, you will be given a project to work on SOC-level performance per watt improvement through memory management innovations. You will be working with the internal SW (eg. OS, Kernel, Framework) and Silicon (eg. RTL, Power, Perf) team members


    • Knowledge in one or more of the following areas,  memory subsystem design, cache memory, LPDDR/DDR/HBM/CXL memory. 
    • Knowledge and experience with common LLM (Large Language Model) workloads.
    • Proficiency in System Verilog, C or C++, scripting languages such as Python.
    • Experience with high-level simulators for performance or power estimation is a plus.
    • Knowledge in server-class GPU/ML architecture is a plus.


    • Responsible for an analytical model of LLM inference and training memory usage
    • Responsible for running the performance simulation to extract the workload's memory footprint and bandwidth requirement. Hence, to derive the energy cost of memory data movement
    • Responsible for identifying memory subsystem capacity or bandwidth bottlenecks and improve the performance and energy efficiency

Minimum Education & Experience

    • Current EE or CS master or Ph.D students with computer architecture backgrounds