Member of Technical Staff (#91842)

Santa Clara, CA

Engineering – Silicon Engineering /

Full-time /

Hybrid

Develop RiVos’s Electrical Analysis methodology and infrastructure to enable the verification

flow of large HPC SoCs. Perform full chip analysis debug and closure of all EA flows, including

IR, IVD, EM for signal and power. Provide input to full chip floor plan and guidance to the

implementation teams throughout the project to enable early convergence and final closure.

Collaborate with Technology team and CAD partners to drive closure targets and signoff criteria.

Design and validate Power Distribution Networks optimized for best PPA in specific Ips.

Expertise in electrical simulation tools, analysis methodologies, and hands-on experience in

ASIC design and verification processes.

1. PDN lead for dual package 5nm, 14LPP chips and responsible for bump planning, providing PDN specifications, SoC full flat EM/IR analysis, IP resistance, ESD placement, respective reviews and its signoff.
2. EMIR convergence issues associated with high performance designs in advanced process nodes (static and dynamic IR driven timing closure).
3. Optimizing power gaters placement which helps in reduction of placement and routing congestion in critical blocks.
4. Collaborating with package, power and physical design teams to meet power targets, IP requirements, ESD and IR drop requirements with package.
5. Experience with industry standard electrical analysis tools (Apache Redhawk, Cadence Voltus).
6. Responsible for PnR implementation of multiple blocks from Netlist to GDSII, guiding peers in closing EM/IR violations and delivering good quality design.
7. Scripting languages: Unix, Perl, and TCL.

$185,775 - $190,000 a year

Worksite: 3315 Scott Blvd, Floor 4, Santa Clara, CA 95054

Applicant Instructions: Email resume to: immigration@rivosinc.com. Must specify job code 91842 in reply. EOE.