Silicon Interposer Design and Flow Development

Mountain View, CA /
Engineering – Platform Engineering (HW) /
A full time position focused on silicon interposer design and flow development from netlist to GDS including place and route, electrical analysis, timing closure, DRC, and LVS. 


    • Interface with top die backend engineer, package substrate designer, Signal Integrity Power Integrity engineer to come up with netlist including multi-die connection, TSV and deep trench capacitors. 
    • Place and route various silicon dies, decaps on interposer.
    • Perform model extraction, electrical analysis, timing closure.
    • Perform DRC, LVS and sign off to tapeout the interposer.
    • Develop the entire backend flow, testing, deployment and maintenance.
    • Interface with EDA vendors to solve issues, evaluate tools and improve the flow.
    • Work with silicon manufacturers to understand design rules, implement verification tools.


    • Domain expertise on EDA tools such as Innovus, Quantus, Tempus, Virtuoso, Nanotime, Calibre.
    • Strong scripting skills in multiple languages (Shell and Tcl, Perl, Python).
    • Experience with revision control tools such as git, Perforce.
    • Deep understanding of silicon interposer technology.
    • Strong technical background in VLSI, ASIC and EDA fundamentals.
    • Background in package substrate design is a plus.
    • Excellent skills in problem solving, written and verbal communication, excellent organization skills, highly self-motivated and self-starter with minimum supervision.
    • Ability to work well in a team and be productive under aggressive schedules.

Education and Experience

    • PhD, Master’s Degree or Bachelor’s Degree in technical subject area with 5+ years experience.