Silicon DFT - Intern

(India) Bangalore, India
Engineering – Silicon Engineering /
Intern /
Hybrid
Internship roles in the area of CPU and SOC DFT design and verification.

Responsibilities

    • Design the DFT features
    • Create test vectors or oversee their creation
    • Collaborate with physical design team to close requirements
    • Validate DFT requirements are being met
    • Work with designers to increase test coverage, debug observability and flexibility
    • Verify post-PD designs meet DFT requirements
    • Work with verification engineers, stepping in to do run tests when needed

Requirements

    • Good knowledge of digital logic design, microprocessor, debug feature, DFT architecture, CPU architecture, and microarchitecture
    • Knowledge of DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump
    • Knowledge of Verilog and experience with simulators and waveform debugging tools
    • Knowledge of Verilog / SystemVerilog
    • Knowledge of Python, , Shell scripting, Makefiles, TCL a plus
    • Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
    • Ability to work well in a team and be productive under aggressive schedules.
Education and Experience
PhD, Master’s or Bachelor’s students in technical subject area.