Accelerator NoC Verification - Full Time
(India) Bangalore, India
Engineering – Silicon Engineering /
Full-time /
Hybrid
Join a cutting-edge and well-funded hardware startup in Silicon Valley as a Verification Engineer. Our mission is to reimagine silicon and create Risc-V based computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.
Requirements
- In-depth knowledge of digital logic design, processor architecture.
- Sophisticated knowledge of SystemVerilog.
- Experienced level knowledge C/C++.Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection.
- Basic knowledge of formal verification methodology is a plus.
- Excellent knowledge of one of the scripting languages such as Python, TCL is a plus.
- Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
- Ability to work well in a team and be productive under aggressive schedules.
- Thorough knowledge of large scale on-chip fabric or on-chip interconnect architecture
- Knowledge of on-chip network protocols: AMBA, AXI, CHI, ACE, Tilelink or APB.
- Familiarity with different on-chip network topologies (ring, mesh, xbar etc).
Responsibilities
- Work closely with architecture and RTL designers on verifying the functional correctness of the design
- Reviewing Architecture and Design Specifications
- Develop test plans and test environments
- Develop tests in assembly, C/C++, SystemVerilog, or vectors according to test plans
- Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered
- Develop checkers in SystemVerilog or C-base transactors to verify the design
- Write assertions and apply formal verification to the designImplementing test benches, generating directed/constrained random tests
- Debugging failures, running simulations, tracking bugs
- Handling schedules and supporting multi-functional engineering effortAssisting in verification flows, automation scripts and regressions
Education and Experience
PhD, Master’s Degree or Bachelor’s Degree in technical subject area.
