Senior Member of Technical Staff (88865)

Santa Clara, CA
Engineering – Silicon Engineering /
Full-time /
Hybrid
Work closely with architects, peer microarchitects and logic designers, verification engineers, and
physical implementation designers to study the architecture specifications and performance features specifications, evaluate their implementation feasibility, tune the features, and write the RTL for the features. Perform the microarchitecture and logic design of the SOC functional and performance features to meet the targets of functionality, performance, timing, area, and power. Integrate the RTL designs from multiple design areas and IPs, regress the integrated models, check the integration requirements, and release models. Focus on methodology and support RTL design. Maintain the RTL model and work with the verification engineers to verify the design and fix the bugs, as well as work with the physical implementors to fix the design for timing and power issues. Collaborate with chip leads to determine other areas to support current or future designs that can benefit from automation and tooling. Apply solid system, fabric, memory, and SOC architecture knowledge to work effectively with physical implementation engineers, verification engineers and architects on assessing the performance impacts from the SOC components and memory subsystem and suggest ideas to improve the overall design. 

Education:

    • Master’s or foreign equivalent in Electrical Engineering or related field (e.g. Electrical and Computer Engineering) 

Experience:

    • 3 years of experience in job offered or related occupation

Special Requirements: Must have at least 1 year of prior work experience in each of the following:

    • Utilizing various ASIC/SoC design tools/techniques, including lint checks, clock and reset domain
    • crossing etc.
    • Working with connectivity checks, RTL generation, formal equivalence verification checks and
    • synthesis flows.
    • Utilizing SystemVerilog programming language.
    • Logic design principles with power, performance, timing and area implications.
    • Automation (using PERL and Python) to enhance the quality of IP handoff and managing design
    • changes.
    • **Telecommuting allowed for this position**
$166,000 - $183,000 a year
Worksite: 3315 Scott Blvd. 4th Floor, Santa Clara, CA 95054
Applicant Instructions: Email resume to: jen@rivosinc.com. Include job code 88865 in reply. EOE.