Analog Mixed Signal Design Verification

(Taiwan) HsinChu, Taiwan
Engineering – Silicon Engineering /
Full-time /
Join a well funded hardware startup as an AMS DV engineer leading the design verification for droop sensing, clocking, PLL, LDO, On-die VRs and PMICs using latest finfet technology nodes. Our mission is to reimagine silicon and disrupt the high performance computing platforms with the RiscV based chiplet designs. 


    • Responsible for performing verification for AMS designs.
    • Create UVM benches for mixed signal blocks and developing test scenarios.
    • Work closely with the architecture and design teams on verification plan and methodology to achieve complete verification coverage
    • Write assertions and checkers for the properties and corner cases
    • Analyze verification coverage and improve the test cases
    • Integrate analogue design IPs from vendors and internal teams and develop verification environments for simulation and emulation


    • Detailed knowledge of verification using SystemVerilog 
    • Experience with creating UVM based testbenches for Analog Mixed-Signal applications
    • Experience with assertion based verification for analog blocks
    • Experience with power aware verification with UPF will be a plus
    • UVM-AMS experience preferred
    • Experience with sv-real preferred
    • Scripting skills in perl / python is preferred
    • Excellent communication skills
    • Team player with an ability to encourage team members

Education & Experience

    • MS (preferred in EE and CE) plus 5 years