CPU Load/Store Microarchitecture and Logic Design
(US&India) Mountain View CA , Austin TX, Portland OR, or Fort Collins CO, Bangalore India /
Engineering – Silicon Engineering /
Rivos is on a mission to build the best RISC-V enterprise systems in the world with class leading performance, power, security and RAS features. We are seeking CPU microarchitecture and design experts in the area of load/store execution and level1 data cache design to join our team in building the best RISC-V CPUs in the world.
- As a CPU microarchitect and design engineer you will be responsible for microarchitecture definition and RTL development of CPU functional, performance and power features.
- Develop microarchitecture specifications and own the RTL development for load/store execution and level1 data cache features
- Work with verification, physical implementation, DFT and firmware teams to deliver a design which meets functional, performance, power and area requirements
- Use domain knowledge to propose and evaluate new features
- Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
- Ability to work well in a team and be productive under aggressive schedules
- Knowledge of computer architecture concepts including load/store architecture, virtual memory, cache coherency and memory consistency models
- Knowledge of modern OoO CPU microarchitectures
- Proficient in SystemVerilog
- Knowledge of RISC-V ISA is a plus but not required
Education and Experience
PhD, Master’s Degree or Bachelor’s Degree in technical subject area.
2+ years of relevant industry experience in CPU load/store execution or other memory subsystem area