DPA Performance Modeling - Intern
Santa Clara, CA, Austin TX
Engineering – Silicon Engineering /
Intern /
On-site
Job description
The Rivos DPA Performance team is responsible for defining performance features for the best-in-class RISCV based systems. An internship position is available to those that seek to grow their skills and work on the next generation of Parallel Programmable Accelerators.
Responsibilities
- As a Performance Modeling intern, you will get to work on a project that will involve some combination of the following:
- Microarchitecture exploration, research, and experimentation
- Correlation between the RTL and performance models, RTL performance debug
- Workload analysis and software optimization involving compilers, libraries, numerics, and other software
- Development of data analysis, visualization, and debug tools, as well as the development of test benches
Requirements
- Architecture and microarchitecture knowledge on CPUs
- Strong C/C++ programming and debugging skills
- Proficiency in scripting languages such as Perl, Python
- Experience with performance modeling simulators is a plus
- Understanding of performance benchmarks and workloads
- Knowledge of SystemVerilog and RTL waveform debugging tools will be a bonus
- Excellent skills in problem-solving, written and verbal communication
- Highly self-motivated
- Ability to work well in a team and be productive under aggressive schedules
Education and Experience
Current EE/CS/CE PhD, Master’s Degree, or Bachelor’s Degree student with a background in computer architecture
