Responsible for performing the microarchitecture and logic design verification of Rivos central

processing unit (CPU). Study the CPU architecture specifications and performance features

specifications, write, and execute test plans, build test benches, and verification infrastructures

for performance features. Manage testbenches and work with micro architect engineers to verify

the design, fix bugs, as well as work with the post-silicon verification engineers to verify silicon

bugs. Execute test plans for features specified in architecture and performance specifications to

build and enhance the verification infrastructures for a focused design area. Discuss design plans

using RTL design language such as Verilog, logic assertion, and verification flow. Design

control systems using programming languages such as System Verilog, C++, and Python. Work

closely with micro architects, logic designers and peer verification engineers to design

pragmatic design verification infrastructure code space that will be an effective verification plan

for complex designs. Test products for functionality and contribute to the overall quality of the

CPU’s functional and performance features focusing on targeted functionality and performance

specification.

$132,100 - $152,000 a year