Principal Formal Verification Engineer

Austin, TX /
Engineering - Hardware – RISC-V /
/ Hybrid
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

CPU Formal Verification Engineer 
CPU verification engineer will be responsible for applying various formal verification techniques to source bugs in specifications and RTL implementation for a high performance data center class CPU 


    • Drive formal verification for multiple CPU blocks by putting together formal test plans and executing on them 
    • Create formal verification flows and deploy techniques that leverage on both industry standard and open-source tools. Drive automation of formal testbenches and ensure they are a part of regressions 
    • Develop assertions, cover properties and connectivity checks as a part of formal verification flows and debug any failures in RTL regressions 
    • Deploy scripts and automation to support formal, review setups and proofs with Microarchitecture and DV engineers 

Experience & Qualifications

    • BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience 
    • Prior experience with formal verification methods and techniques 
    • Strong knowledge of computer architecture with some experience on CPU, GPU, Cache designs 
    • Hands-on experience with formal verification tools such as Jasper, VC-Formal, Yosys, IFV, Questa, etc. 
    • Proficiency in programing/scripting languages 
    • Strong experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator), experience capturing design specification in a temporal assertion language such as SVA 
    • Strong problem solving and debug skills for complex logic and digital designs 
Multiple geographies: Santa Clara, Austin, Bangalore (India), Portland, Cambridge (UK), Remote (US) 

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been sanctioned by the U.S. government.

As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency information and/or documentation will be required and considered as Tenstorrent moves through the employment process.